The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a semiconductor device having a transistor and a method for fabrication thereof. Merely by way of example, the invention has been applied to a field effect transistor (FET) device having a gate-all-around cylindrical (GAAC) nanowire. As an example, the FET is based on a silicon-on-insulator (SOI) wafer substrate and method for the manufacture thereof. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility.
However, making devices smaller is very challenging, as each process used in IC fabrication may have certain limits. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example of such a limit is that for CMOS processes and technology at reduced gate lengths conventional CMOS device have increasing difficulty in maintaining high drive currents with low off-current leakage and threshold voltage stability as well. The short-channel effect becomes a big hurdle to further scale down the conventional CMOS devices. This results in a degradation of the device performance and determines the limits of miniaturization. Over the past, various conventional techniques have been developed to overcome the abovementioned limits. Unfortunately, these techniques have often been inadequate.
Therefore, it is desirable to have an improved gate structure for MOS devices and processes thereof.